This invention relates to programmable logic devices (“PLDs”), and more particularly to a new architecture for the input/output (I/O) circuitry which couples the PLDs to external circuitry.
Programmable logic devices are integrated circuits which are able to implement combinational and/or sequential digital functions which may be defined by a designer and programmed into the device. Thus, PLDs may be configured by a user to implement any Boolean expression or registered function with built-in logic structures. Once a PLD is configured, the user must connect the PLD to external circuitry which provides input signals to, and receives output signals from, the PLD.
One deficiency of conventional PLDs and their I/O circuitry is that each PLD must be configured to operate with specific external circuitry. For example, if a user utilizes Transistor-to-Transistor Logic (TTL) or CMOS external circuitry, the PLD must be configured to provide the appropriate drive signals. However, the selection of open drain logic may require different drive parameters and thus, a different PLD, even though the basic PLD is substantially the same. This deficiency is even more apparent in view of the programmable nature of PLDs and the flexibility provided to the end users.
Further, the nature of PLDs, as semiconductor devices, is that they are susceptible to a wide range of potential hazards, such as electrostatic discharge (ESD). To avoid these potential problems, care must be taken in connecting the PLD pins to external circuitry. Any pins which are used as input pins should preferably be driven by an active source (including bi-directional pins during input operations). Additionally, unused pins are typically tied to ground to avoid the potential of additional DC current and noise being introduced into the circuits.
Output loading of the PLD I/O pins is typically resistive and/or capacitive. Resistive loading exists where the device output sinks or sources a current during steady-state operation (e.g., TTL inputs, terminated buses, and discrete bipolar transistors). Capacitive loading typically occurs from packaging and printed circuit board traces. Further, an important design consideration of the interface between the PLD and external circuitry is that the target device can supply both the current and speed necessary for the given loads.
Various attempts have also been made at providing interface circuitry that operates at lower power levels, for example, the Gunning Transistor Logic (GTL) interface described in Gunning U.S. Pat. No. 5,023,488. GTL interface drivers typically operate with a voltage swing on the order of about 0.8 volts to 1.2 volts, which are intended to drive a CMOS binary communications bus. Another interface, High-Speed Transistor Logic (HSTL) typically operates with a voltage swing of about a predetermined voltage plus 0.050 volts to the predetermined voltage minus 0.050 volts and at relatively higher switching frequencies than GTL (for terminated HSTL, the predetermined voltage is the termination voltage, while non-terminated HSTL uses a reference voltage).
One deficiency of Gunning and other known driver circuitry is the limited scope with which the circuitry may be used. A PLD having GTL drivers must interface with a GTL bus. A PLD having TTL drivers must interface with a TTL bus or discrete TTL components. A PLD having HSTL drivers must interface with a HSTL bus or discrete HSTL components.
In view of the foregoing, it would be desirable to be able to provide an I/O architecture which provides the capability to drive multiple logic standards.
It would also be desirable to be able to provide an I/O architecture having the capability to selectively drive any one of multiple logic standards.
It would further be desirable to be able to provide an I/O architecture which may be programmed by a user to select any one of several logic standards, such that a single PLD may be used with external circuitry that operates at different logic levels.